Modern semiconductor based integrated circuits (ICs) are incredibly complex and contain millions of circuit devices, such as transistors, and millions of interconnections between the circuit devices. Designing, testing, and verifying the functionality of such complex circuits cannot be accomplished manually, and circuit designers use computer based Electronic Design Automation (EDA) tools for schematics, layouts, simulation, and verification of the complex circuits. In additional to designing an IC with the correct functionally, another equally significant function of the EDA tools is to optimize the IC design. One of the optimization targets is to reduce power consumption by the fabricated IC. In addition to consuming less power and offering a longer battery life, an IC with reduced power consumption generates less heat and does not require elaborate heat dissipation mechanism. In this age of portable and yet incredibly complex electronics, ICs with reduced power consumption have therefore been increasingly relevant and sought after.
To allow a circuit designer to optimize power consumption, EDA tools offer power consumption verification of an IC design. Conventional EDA tools generally use vector-based power analysis, in which an IC design is simulated by feeding a test vector of inputs. The simulation then generates value change dump (VCD) files based on the simulation. The VCD files can be parsed to determine the current flow through circuit instances in the IC design. The current flow can be then used to calculate the power consumed by the circuit instances. However, as the complexity of ICs has been increasing exponentially, vector-based power analysis has become computationally expensive as the entire IC has to be simulated for multiple clock-cycles to generate the VCD files. Furthermore, significant computation resources have to be expended to parse the generated VCD files, determine the current flowing through various circuit instances, and calculate the power consumed by the IC.
Vectorless power analysis can be a computationally efficient alternative for a full-fledged vector-based power analysis. However, conventional EDA tools offer vectorless power analysis based on an assumption of the worst case scenario. More specifically, conventional EDA tools assume that all of the integrated clock gaters (ICGs, used to selectively turn off unrequired portions of the IC) are turned on all the time. In other words, conventional EDA tools assume that all portions of the IC to be active for a power analysis, which leads to an overly pessimistic power consumption assessment. Such pessimistic assessment may not present the true behavioral picture of the IC. Furthermore, the pessimistic assessment may lead the conventional EDA tools and/or the circuit designer to undertake unnecessary optimizations to further reduce power consumption.
What is therefore required is an EDA tool that breaks the aforementioned worst case scenario assumption that the entire clock network is toggling and can select particular ICGs and the corresponding logic cones to be turned on for a vectorless power analysis. What is also required is an EDA tool that provides a more realistic behavioral picture of the IC in terms of power consumption and offers a vectorless power analysis that closely approximates vector-based power analysis.